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www.gennum.com gs1531 hd-linx? ii multi-rate serializer gs1531 data sheet 30573 - 4 july 2005 1 of 49 key features ? smpte 292m and smpte 259m-c compliant scrambling and nrz nrzi encoding (with bypass) ? dvb-asi sync word insertion and 8b/10b encoding ? superior rejection of jitter on input pclk ? user selectable addition al processing features including: ? crc, anc data checksum, and line number calculation and insertion ? trs and edh packet generation and insertion ? illegal code remapping ? internal flywheel for noise immune trs generation ? 20-bit / 10-bit cmos parallel input data bus ? 148.5mhz / 74.25mhz / 27mhz / 13.5mhz parallel digital input ? automatic standards detection and indication ? 1.8v core power supply and 3.3v charge pump power supply ? 3.3v digital i/o supply ? jtag test interface ? available in a pb-free package ? small footprint (11mm x 11mm) applications ? smpte 292m serial digital interfaces ? smpte 259m-c serial digital interfaces ? dvb-asi serial digital interfaces description the gs1531 is a multi-standard serializer with an integrated cable driver. when used in conjunction with the go1525 voltage controlle d oscillator, a transmit solution can be realized for hd-sdi, sd-sdi and dvb-asi applications. the device features an inte rnal pll, which can be configured for loop bandwidth as narrow as 100khz. thus the gs1531 can tolerate substantive jitter on the input pclk and still provid e output jitter well within smpte specification. connec t the output clocks from gennum?s gs4911 clock generator directly to the gs1531?s pclk input and configure the gs1531?s loop bandwidth accordingly. in addition to serializing the input, the gs1531 performs nrz-to-nrzi encoding and scrambling as per smpte 292m/259m-c when operating in smpte mode. when operating in dvb-asi mode, the device will insert k28.5 sync characters and 8b/10b encode the data prior to serialization. parallel data inputs are prov ided for 10-bit multiplexed or 20-bit demultiplexed formats at both hd and sd signal rates. an appropriate parallel clock input signal is also required. the integrated cable driver features an output mute on loss of parallel clock, high impedance mode, adjustable signal swing, and automatic dual slew rate selection depending on hd/sd operational requirements. the gs1531 also includes a range of data processing functions including automatic standards detection and edh support. the device can also insert trs signals, calculate and insert line numbers and crc?s, re-map illegal code words and inse rt smpte 352m payload identifier packets. all processing features are optional and may be enabled/disabled via external control pin(s) and/or host interface programming.
gs1531 data sheet 30573 - 4 july 2005 2 of 49 gs1531 functional block diagram sdo sdo sdo_en/dis rset cp_cap h v f din[19:0] ioproc_en/dis dvb_asi i/o buffer & demux smpte 352m generation trs insertion, line number insertion, crc insertion, data blank, code- re-map and flywheel dvb-asi bypass reset_trst reset host interface / jtag test cs_tms sclk_tck sdin_tdi sdout_tdo jtag/host locked v co vco lf lb_cont vco_vcc vco_gnd sd/hd 20bit/10bit dvb-asi sync word insert & 8b/10b encode edh generation & smpte scramble pclk blank detect_trs smpte_bypass phase detector, charge pump, vco control & power supply p -> s sd/hd
gs1531 data sheet 30573 - 4 july 2005 3 of 49 contents key features.................................................................................................................1 applications................................................................................................................... 1 description .................................................................................................................... 1 1. pin out .................................................................................................................... .5 1.1 pin assignment ...............................................................................................5 1.2 pin descriptions ..............................................................................................6 2. electrical characteristics ........................................................................................13 2.1 absolute maximum rating s ..........................................................................13 2.2 dc electrical characteristics ............. ...........................................................13 2.3 ac electrical characteristics........... ..............................................................14 2.4 solder reflow profiles...................................................................................16 3. input/output circuits ..............................................................................................17 3.1 host interface maps......................................................................................19 3.1.1 host interface map (read only r egisters) ....... .............. ........... .........20 3.1.2 host interface map (r/w confi gurable registers) .............................21 4. detailed description ...............................................................................................22 4.1 functional overview .....................................................................................22 4.2 parallel data inputs.......................................................................................22 4.2.1 parallel input in smpte mode............................................................23 4.2.2 parallel input in dvb-asi mode..........................................................23 4.2.3 parallel input in data-through m ode .......... .............. .............. ............23 4.2.4 parallel input clock (pclk) ................................................................24 4.3 smpte mode................................................................................................25 4.3.1 internal flywheel........................ .........................................................25 4.3.2 hvf timing signal extraction .............................................................25 4.4 dvb-asi mode..............................................................................................27 4.4.1 control signal inputs ..........................................................................27 4.5 data-through mode .......... .............. .............. .............. .............. ........... .........28 4.6 additional processing functions ........ ...........................................................28 4.6.1 input data blank .................................................................................28 4.6.2 automatic video standard detection..................................................28 4.6.3 packet generation and insertion .. .............. .............. .............. ............30 4.7 parallel-to-serial conversion .......................................................................37 4.8 serial digital data pll.................... ..............................................................38 4.8.1 external vco......................................................................................38 4.8.2 lock detect output .............................................................................38 4.9 serial digital output ......................................................................................39 4.9.1 output swing ......................................................................................39 4.9.2 serial digital output mute...................................................................39 4.10 gspi host interface ....................................................................................40
gs1531 data sheet 30573 - 4 july 2005 4 of 49 4.10.1 command word description.......... .............. .............. .............. .........40 4.10.2 data read and write timing ............................................................41 4.10.3 configuration and status registers ..................................................42 4.11 jtag...........................................................................................................42 4.12 device power up ........................................................................................44 4.13 device reset...............................................................................................44 5. application reference design .................. ..............................................................45 5.1 typical application circuit .............................................................................45 6. references & relevant standards ........... .............. .............. .............. ........... .........46 7. package & ordering informa tion............................................................................47 7.1 package dimensions ....................................................................................47 7.2 packaging data.............................................................................................48 7.3 ordering information .....................................................................................48 8. revision history .....................................................................................................49
gs1531 data sheet 30573 - 4 july 2005 5 of 49 1. pin out 1.1 pin assignment 1 3 2 45 6 7 8 9 10 a b c d e f g h j k locked pclk lb_ cont nc din19 din18 din17 din16 din14 din12 din10 din8 din6 din4 din2 din1 din15 din13 din11 din9 din7 din5 din3 din0 sd/hd io_vdd io_vdd io_gnd blank h io_vdd core _vdd io_gnd core _vdd core _gnd core _gnd detect _trs dvb_asi smpte_ bypass nc nc 20bit/ 10bit sdin _tdi sclk _tck sdout _tdo cs_ tms nc nc nc cd_vdd rset nc nc nc nc nc nc nc nc nc cp_cap sdo sd0 vco_ vcc vco_ gnd lf vco vco cp_vdd cp_gnd pd_vdd pd_gnd nc nc nc nc v io_gnd cd_gnd f nc nc nc nc nc nc nc nc nc nc rsv nc nc nc nc nc jtag/ host sdo_en /dis reset _trst ioproc _en/dis
gs1531 data sheet 30573 - 4 july 2005 6 of 49 1.2 pin descriptions table 1-1: pin descriptions pin number name timing type description a1 lf analog output control voltage to external vo ltage controlled oscillator. nominally +1.25v dc. a2 vco_vcc ? output power power supply for the external voltage controlled oscillator. connect to pin 7 of the go1525. this pin is an output. should be isolated from all other power supplies. a3 vco_gnd ? output power ground reference for the external voltage controlled oscillator. connect to pins 2, 4, 6, and 8 of the go1525. this pin is an output. should be isolated from all other grounds. a4, a5 vco , vco analog input differential inputs for the ex ternal vco reference signal. for single ended devices such as the go1525, vco should be ac coupled to vco_gnd. vco is nominally 1.485ghz. a6, b5, b6, c1, c4, c5, c6, c7, c8, d1, d2, d3, d4, d7, d8, e1, e2, e3, e7, f2, f3, f7, g1, g2, g3, g7, h1, h2, h3, h7, j1, j2, j3, j4 nc ? ? no connect. a7 pclk ? input parallel data bus clock signal levels are lvcmos/lvttl compatible. hd 20-bit mode pclk = 74.25mhz or 74.25/1.001mhz hd 10-bit mode pclk = 148.5mhz or 148.5/1.001mhz sd 20-bit mode pclk = 13.5mhz sd 10-bit mode pclk = 27mhz a8, e8, k8 io_vdd ? power power supply connection for digital i/o buffers. connect to +3.3v dc digital.
gs1531 data sheet 30573 - 4 july 2005 7 of 49 a10, a9, b10, b9, c10, c9, d10, d9, e10, e9 din[19:10] synchronous with pclk input parallel data bus signal levels are lvcmos/lvttl compatible. din19 is the msb and din10 is the lsb. hd 20-bit mode sd/hd = low 20bit/10bit = high luma data input in smpte mode smpte_bypass = high dvb_asi = low data input in data-through mode smpte_bypass = low dvb_asi = low hd 10-bit mode sd/hd = low 20bit/10bit = low multiplexed luma and chroma data input in smpte mode smpte_bypass = high dvb_asi = low data input in data-through mode smpte_bypass = low dvb_asi = low sd 20-bit mode sd/hd = high 20bit/10bit = high luma data input in smpte mode smpte_bypass = high dvb_asi = low data input in data-through mode smpte_bypass = low dvb_asi = low dvb-asi data input in dvb-asi mode smpte_bypass = low dvb_asi = high sd 10-bit mode sd/hd = high 20bit/10bit = low multiplexed luma and chroma data input in smpte mode smpte_bypass = high dvb_asi = low data input in data through mode smpte_bypass = low dvb_asi = low dvb-asi data input in dvb-asi mode smpte_bypass = low dvb_asi = high b1 cp_cap analog input pll lock time constant capacitor connection. b2 cp_vdd ? power power supply connection for the charge pump. connect to +3.3v dc analog. b3 cp_gnd ? power ground connection for the charge pump. connect to analog gnd. b4 lb_cont analog input control voltage to set the loop bandwidth of the integrated reclocker. b7 detect_trs non synchronous input control signal input signal levels are lvcmos/lvttl compatible. used to select the timing mode of the device. when set high, the device will lock the internal flywheel to the embedded trs timing signals in the parallel input data. when set low, the device will lock the internal flywheel to the externally supplied h, v, and f input signals. table 1-1: pin descriptions (continued) pin number name timing type description
gs1531 data sheet 30573 - 4 july 2005 8 of 49 b8, f8, j8 io_gnd ? power ground connection for di gital i/o buffers. connect to digital gnd. c2 pd_vdd ? power power supply connection for the phase detector. connect to +1.8v dc analog. c3 pd_gnd ? power ground connection for t he phase detector. connect to analog gnd. d5 dvb_asi non synchronous input control signal input signal levels are lvcmos/lvttl compatible. when set high in conjunction with sd/hd = high and smpte_bypass = low, the device will be configured to operate in dvb-asi mode. when set low, the device will not support the encoding of received dvb-asi data. d6 locked synchronous with pclk output status signal output signal levels are lvcmos / lvttl compatible. the locked signal will be high w henever the device has correctly received and locked to smpte compliant data in smpte mode or dvb-asi compliant data in dvb-asi mode, or when the device has achieved lock in data-through mode. it will be low otherwise. e4 sd/hd non synchronous input control signal input signal levels are lvcmos/lvttl compatible. when set low, the device will be conf igured to transmit signal rates of 1.485gb/s or 1.485/1.001gb/s only. when set high, the device will be conf igured to transmit signal rates of 270mb/s only. e5, f5 core_gnd ? power ground connection for the di gital core logic. connect to digital gnd. e6, f6 core_vdd ? power power supply connection for t he digital core logic. connect to +1.8v dc digital. f1 rsv ? ? connect to analog gnd. f4 20bit/10bit non synchronous input control signal input signal levels are lvcmos/lvttl compatible. used to select the input data bus width in smpte or data-through modes. this signal is ignored in dvb-asi mode. when set high, the parallel input will be 20-bit demultiplexed data. when set low, the parallel input will be 10-bit multiplexed data. table 1-1: pin descriptions (continued) pin number name timing type description
gs1531 data sheet 30573 - 4 july 2005 9 of 49 f10, f9, g10, g9, h10, h9, j10, j9, k10, k9 din[9:0] synchronous with pclk input parallel data bus signal levels are lvcmos/lvttl compatible. din9 is the msb and din0 is the lsb. hd 20-bit mode sd/hd = low 20bit/10bit = high chroma data input in smpte mode smpte_bypass =high dvb_asi = low data input in data-through mode smpte_bypass = low dvb_asi = low hd 10-bit mode sd/hd = low 20bit/10bit = low high impedance in all modes. sd 20-bit mode sd/hd = high 20bit/10bit = high chroma data input in smpte mode smpte_bypass = high dvb_asi = low data input in data-through mode smpte_bypass = low dvb_asi = low high impedance in dvb-asi mode smpte_bypass = low dvb_asi = high sd 10-bit mode sd/hd = high 20bit/10bit = low high impedance in all modes. g4 ioproc_en/dis non synchronous input control signal input signal levels are lvcmos/lvttl compatible. used to enable or disable i/o processing features. when set high, the following i/o proc essing features of the device are enabled: ? edh packet generation and insertion (sd-only) ? smpte 352m packet generation and insertion ? anc data checksum calculation and insertion ? line-based crc generation and insertion (hd-only) ? line number generation and insertion (hd-only) ? trs generation and insertion ? illegal code remapping to enable a subset of these features, keep ioproc_en/dis high and disable the individual feature(s) in the ioproc_disable register accessible via the host interface. when set low, the i/o processing feat ures of the device are disabled, regardless of whether the features are enabled in the ioproc_disable register. table 1-1: pin descriptions (continued) pin number name timing type description
gs1531 data sheet 30573 - 4 july 2005 10 of 49 g5 smpte_bypass non synchronous input control signal input signal levels are lvcmos/lvttl compatible. when set high in conjunction with dvb_asi = low, the device will be configured to operate in smpte mode. all i/o processing features may be enabled in this mode. when set low, the device will not s upport the scrambling or encoding of received smpte data. no i/o processing features will be available. g6 reset_trst non synchronous input control signal input signal levels are lvcmos/lvttl compatible. used to reset the internal operating conditions to default settings and to reset the jtag test sequence. host mode (jtag/host = low) when asserted low, all functional bloc ks will be set to default conditions and all input and output signals become high impedance, including the serial digital outputs sdo and sdo. must be set high for normal device operation. jtag test mode (jtag/host = high) when asserted low, all functional bloc ks will be set to default and the jtag test sequence will be held in reset. when set high, normal operation of the jtag test sequence resumes. g8 blank synchronous with pclk input control signal input signal levels are lvcmos/lvttl compatible. used to enable or disable input data blanking. when set low, the luma and chroma input data is set to the appropriate blanking levels. horizontal and vertical ancillary spaces will also be set to blanking levels. when set high, the luma and chroma input data pass through the device unaltered. h4 cs _tms synchronous with sclk_tck input control signal input signal levels are lvcmos/lvttl compatible. chip select / test mode select host mode (jtag/host = low) cs _tms operates as the host interface chip select, cs , and is active low. jtag test mode (jtag/host = high) cs _tms operates as the jtag test mode select, tms, and is active high. note: if the host interface is not being used, tie this pin high. h5 sclk_tck non synchronous input control signal input signal levels are lvcmos/lvttl compatible. serial data clock / test clock. host mode (jtag/host = low) sclk_tck operates as the host in terface burst clock, sclk. command and data read/write words are clock ed into the device synchronously with this clock. jtag test mode (jtag/host = high) sclk_tck operates as the jtag test clock, tck. note: if the host interface is not being used, tie this pin high. table 1-1: pin descriptions (continued) pin number name timing type description
gs1531 data sheet 30573 - 4 july 2005 11 of 49 h6 sdout_tdo synchronous with sclk_tck output control signal output signal levels are lvcmos/lvttl compatible. serial data output / test data output host mode (jtag/host = low) sdout_tdo operates as the host interface serial output, sdout, used to read status and configuration information from the internal registers of the device. jtag test mode (jtag/host = high) sdout_tdo operates as the jtag test data output, tdo. h8 h synchronous with pclk input control signal input signal levels are lvcmos/lvttl compatible. used to indicate the portion of the video line containing active video data when detect_trs is set low. the device will set the h bit in all outgoing trs signals for the entire period that the h input signal is high (ioproc_en/dis must also be high). h signal timing is configurable via the h_config bit of the ioproc_disable register, accessible via the host interface. active line blanking (h_config = 0 h ) the h signal should be set high for th e entire horizontal blanking period, including the eav and sav trs words, and low otherwise. this is the default setting. trs based blanking (h_config = 1 h ) the h signal should be set high for the entire horizontal blanking period as indicated by the h bit in the received trs id words, and low otherwise. j5 sdo_en/dis non synchronous input control signal input signal levels are lvcmos/lvttl compatible. used to enable or disable the serial digital output stage. when set low, the serial digital output signals sdo and sdo are disabled and become high impedance. when set high, the serial digital output signals sdo and sdo are enabled. j6 sdin_tdi synchronous with sclk_tck input control signal input signal levels are lvcmos/lvttl compatible. serial data in / test data input host mode (jtag/host = low) sdin_tdi operates as the host interface serial input, sdin, used to write address and configuration information to the internal registers of the device. jtag test mode (jtag/host = high) sdin_tdi operates as the jtag test data input, tdi. note: if the host interface is not being used, tie this pin high. table 1-1: pin descriptions (continued) pin number name timing type description
gs1531 data sheet 30573 - 4 july 2005 12 of 49 j7 v synchronous with pclk input control signal input signal levels are lvcmos/lvttl compatible. used to indicate the portion of the video field / frame that is used for vertical blanking when detect_trs is set low. the device will set the v bit in all outgoing trs signals for the entire period that the v input signal is high (ioproc_en/dis must also be high). the v signal should be set high for the entire vertical blanking period and should be set low for all lines outside of the vertical blanking interval. the v signal is ignored when detect_trs = high. k1 rset analog input used to set the serial digi tal output signal amplitude. connect to cd_vdd through 281 +/- 1% for 800mv p-p single-ended output swing. k2 cd_vdd ? power power supply connection for t he serial digital cable driver. connect to +1.8v dc analog. k3, k4 sdo, sdo analog output serial digital output signal operating at 1.485gb/s, 1.485/1.001gb/s, or 270mb/s. the slew rate of these outputs is automatically controlled to meet smpte 292m and 259m requirements according to the setting of the sd/hd pin. k5 cd_gnd ? power ground connection for the serial digital cable driver. connect to analog gnd. k6 jtag/host non synchronous input control signal input signal levels are lvcmos/lvttl compatible. used to select jtag test mode or host interface mode. when set high, cs _tms, sdout_tdo, sdi_tdi and sclk_tck are configured for jtag boundary scan testing. when set low, cs _tms, sdout_tdo, sdi_tdi and sclk_tck are configured as gspi pins for normal host interface operation. k7 f synchronous with pclk input control signal input signal levels are lvcmos/lvttl compatible. used to indicate the odd / even field of the video signal when detect_trs is set low. the device wi ll set the f bit in all outgoing trs signals for the entire period that the f input signal is high (ioproc_en/dis must also be high). the f signal should be set high for the entire period of field 2 and should be set low for all lines in field 1 and for all lines in progressive scan systems. the f signal is ignored when detect_trs = high. table 1-1: pin descriptions (continued) pin number name timing type description
gs1531 data sheet 30573 - 4 july 2005 13 of 49 2. electrical characteristics 2.1 absolute maximum ratings 2.2 dc electrical characteristics parameter value/units supply voltage core -0.3v to +2.1v supply voltage i/o -0.3v to +4.6v input voltage range (any input) -2.0v to + 5.25v ambient operating temperature -20c < t a < 85c storage temperature -40c < t stg < 125c esd protection on all pins (see note 1) 1kv notes: 1. hbm, per jesda-114b. table 2-1: dc electrical characteristics t a = 0c to 70c, unless otherwise specified. parameter symbol conditions min typ max units test level notes system operation temperature range t a ?0?70c31 digital core supply voltage core_vdd ? 1.71 1.8 1.89 v 3 1 digital i/o supply voltage io_vdd ? 3.13 3.3 3.47 v 3 1 charge pump supply voltage cp_vdd ? 3.13 3.3 3.47 v 3 1 phase detector supply voltage pd_vdd ? 1.71 1.8 1.89 v 3 1 input buffer supply voltage buff_vdd ? 1.71 1.8 1.89 v 3 1 cable driver supply voltage cd_vdd ? 1.71 1.8 1.89 v 3 1 external vco supply voltage output vco_vcc ? 2.25 ? 2.75 v 1 ? +1.8v supply current i 1v8 sdo enabled ? ? 245 ma 3 3 +3.3v supply current i 3v3 ???45ma34 to ta l d e v i c e p o w e r p d sdo enabled ? ? 590 mw 3 ?
gs1531 data sheet 30573 - 4 july 2005 14 of 49 2.3 ac electrical characteristics digital i/o input logic low v il ??? 0.8v4? input logic high v ih ?2.1??v4? output logic low v ol +8ma ? 0.2 0.4 v 4 ? output logic high v oh -8ma io_vdd - 0.4 ? ? v 4 ? input rset voltage v rset rset=281 0.54 0.6 0.66 v 1 2 output output common mode voltage v cmout 75 load, rset=281 , sd and hd 0.8 1.0 1.2 v 1 ? test levels 1. production test at room temperature and nominal supply voltage with guardbands for supply and temperature ranges. 2. production test at room temperature and nominal supply voltage with guardbands for supply and temperature ranges using correlated test. 3. production test at room temperature and nominal supply voltage. 4. qa sample test. 5. calculated result based on level 1, 2, or 3. 6. not tested. guaranteed by design simulations. 7. not tested. based on characterization of nominal parts. 8. not tested. based on existing design/characterization data of similar product. 9. indirect test. notes 1. all dc and ac electrical para meters within specification. 2. set by the value of the rset resistor. 3. sum of all 1.8v supplies. 4. sum of all 3.3v supplies. table 2-1: dc electrical characteristics (continued) t a = 0c to 70c, unless otherwise specified. parameter symbol conditions min typ max units test level notes table 2-2: ac electrical characteristics t a = 0c to 70c, unless otherwise shown parameter symbol conditions min typ max units test level notes system device latency ? 10-bit sd ? 21 ? pclk 8 ? ? 20-bit hd ? 19 ? pclk 8 ? ? dvb-asi ? 11 ? pclk 8 ? reset pulse width t reset ?1??ms81
gs1531 data sheet 30573 - 4 july 2005 15 of 49 parallel input parallel clock frequency f pclk ? 13.5 ? 148.5 mhz 4 ? parallel clock duty cycle dc pclk ?40? 60%6? input data setup time t su ?2.0??ns5? input data hold time t ih ?1.5??ns5? serial digital output serial output data rate dr sdo ? ? 1.485 ? gb/s 1 ? ? ? 1.485/1.001 ? gb/s 9 ? ? ?270?mb/s1? serial output swing v sdd rset = 281 75 load 650 800 950 mvp-p 1 ? serial output rise time 20% ~ 80% tr sdo hd signal ? ? 260 ps 1 ? tr sdo sd signal 400 550 1500 ps 1 ? serial output fall time 20% ~ 80% tf sdo hd signal ? ? 260 ps 1 ? tf sdo sd signal 400 550 1500 ps 1 ? serial output intrinsic jitter t ij pseudorandom and pathological hd signal ?90125ps5? t ij pseudorandom and pathological sd signal ?270350ps5 ? gspi gspi input clock frequency f sclk ???6.6mhz8? gspi input clock duty cycle dc sclk ?40?60%8? gspi input data setup time ? ? 0 ? ? ns 8 ? gspi input data hold time ? ? 1.43 ? ? ns 8 ? gspi output data hold time ? ? 2.1 ? ? ns 8 ? gspi output data delay time ? ? ? ? 7.27 ns 8 ? test levels 1. production test at room temperature and nominal supply voltage with guardbands for supply and temperature ranges. 2. production test at room temperature and nominal supply voltage with guardbands for supply an d temperature ranges using correlated test. 3. production test at room temperature and nominal supply voltage. 4. qa sample test. 5. calculated result based on level 1, 2, or 3. 6. not tested. guaranteed by design simulations. 7. not tested. based on characterization of nominal parts. 8. not tested. based on existing design/characterization data of similar product. 9. indirect test. notes 1. see device power up on page 44 , figure 4-12 . table 2-2: ac electrical characteristics (continued) t a = 0c to 70c, unless otherwise shown parameter symbol conditions min typ max units test level notes
gs1531 data sheet 30573 - 4 july 2005 16 of 49 2.4 solder reflow profiles the gs1531 is available in a pb or pb-free package. it is recommended that the pb package be soldered with pb paste us ing the standard eutectic profile shown in figure 2-1 , and the pb-free package be soldered with pb-free paste using the reflow profile shown in figure 2-2 . note: it is possible to so lder a pb-free package with pb paste using a standard eutectic profile with a reflow temperature maintained at 245 o c ? 250 o c. figure 2-1: standard eutectic solder re flow profile (pb package, pb paste) figure 2-2: maximum pb-free solder refl ow profile (pb-free package, pb-free paste) 25?c 100?c 150?c 183?c 230?c 220?c time temperature 6 min. max 120 sec. max 60-150 sec. 10-20 sec. 3?c/sec max 6?c/sec max 25?c 150?c 200?c 217?c 260?c 250?c time temperature 8 min. max 60-180 sec. max 60-150 sec. 20-40 sec. 3?c/sec max 6?c/sec max
gs1531 data sheet 30573 - 4 july 2005 17 of 49 3. input/output circuits all resistors in ohms, all capacitors in farads, unless otherwise shown. figure 3-1: serial digital output figure 3-2: vco control output & pll lock time capacitor figure 3-3: pclk input sdo sdo 300 cp_cap lf vdd 42k 63k pclk
gs1531 data sheet 30573 - 4 july 2005 18 of 49 figure 3-4: vco input figure 3-5: pll loop bandwidth control vdd 25 25 vco vco 1.5k 5k 865mv 7.2k lb_cont
30573 - 4 july 2005 19 of 49 gs1531 data sheet 3.1 host interface maps register name address 15 14 13 12 11 10 9 8 7 6 5 43 210 line_352m_f2 1ch not used not used not used not used not usedb10b9b8b7b6b5b4b3b2b1b0 line_352m_f1 1bh not used not used not used not used not usedb10b9b8b7b6b5b4b3b2b1b0 1ah ff_line_end_f1 19h not used not used not used not used not used not used b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 ff_line_start_f1 18h not used not used not used not used not used not used b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 ff_line_end_f0 17h not used not used not used not used not used not used b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 ff_line_start_f0 16h not used not used not used not used not used not used b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 ap_line_end_f1 15h not used not used not used not used not used not used b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 ap_line_start_f1 14h not used not used not used not used not used not used b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 ap_line_end_f0 13h not used not used not used not used not used not used b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 ap_line_start_f0 12h not used not used not used not used not used not used b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 raster_structure4 11h not used not used not used not used not usedb10b9b8b7b6b5b4b3b2b1b0 raster_structure3 10h not used not used not used not used not usedb10b9b8b7b6b5b4b3b2b1b0 raster_structure2 0fh not used not used not used not used b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 raster_structure1 0eh not used not used not used not used b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 0dh 0ch video_format_b 0bh vf4-b7 vf4-b6 vf4-b5 vf4-b4 vf4-b3 vf4-b2 vf4-b1 vf4-b0 vf3-b7 vf3-b6 vf3-b5 vf3-b4 vf3-b3 vf3-b2 vf3-b1 vf3-b0 video_format_a 0ah vf2-b7 vf2-b6 vf2-b5 vf2-b4 vf2-b3 vf2-b2 vf2-b1 vf2-b0 vf1-b7 vf1-b6 vf1-b5 vf1-b4 vf1-b3 vf1-b2 vf1-b1 vf1-b0 09h 08h 07h 06h 05h video_standard 04h not used vds-b4 vds-b3 vds-b2 vds-b1 vds-b0 int_prog std_ lock not used not used not used not used not used not used not used not used 03h edh_flag 02h not used anc-ues anc-ida anc-idh anc-eda anc-edh ff-ues ff-ida ff-idh ff-eda ff-edh ap-ues ap-ida ap-idh ap-eda ap-edh 01h ioproc_disable 00h not used not used not used not used not used not used not used h_config not used 352m_ins illegal_re map edh_crc_in s anc_ csum_ins crc_ins lnum_ ins trs_ins
30573 - 4 july 2005 20 of 49 gs1531 data sheet 3.1.1 host interface map (r ead only registers) register nameaddress1514131211109876543210 1ch 1bh 1ah 19h 18h 17h 16h 15h 14h 13h 12h raster_structure4 11h b10b9b8b7b6b5b4b3b2b1b0 raster_structure3 10h b10b9b8b7b6b5b4b3b2b1b0 raster_structure2 0fh b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 raster_structure1 0eh b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 0dh 0ch 0bh 0ah 09h 08h 07h 06h 05h video_standard 04h vds-b4 vds-b3 vds-b2 vds-b1 vds-b0 int_prog std_ lock 03h 02h 01h 00h
30573 - 4 july 2005 21 of 49 gs1531 data sheet 3.1.2 host interface map (r/w configurable registers) register nameaddress1514131211109876543210 line_352m_f2 1ch b10b9b8b7b6b5b4b3b2b1b0 line_352m_f1 1bh b10b9b8b7b6b5b4b3b2b1b0 1ah ff_line_end_f1 19h b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 ff_line_start_f1 18h b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 ff_line_end_f0 17h b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 ff_line_start_f0 16h b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 ap_line_end_f1 15h b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 ap_line_start_f1 14h b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 ap_line_end_f0 13h b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 ap_line_start_f0 12h b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 11h 10h 0fh 0eh 0dh 0ch video_format_b 0bh vf4-b7 vf4-b6 vf4-b5 vf4-b4 vf4-b3 vf4-b2 vf4-b1 vf4-b0 vf3-b7 vf3-b6 vf3-b5 vf3-b4 vf3-b3 vf3-b2 vf3-b1 vf3-b0 video_format_a 0ah vf2-b7 vf2-b6 vf2-b5 vf2-b4 vf2-b3 vf2-b2 vf2-b1 vf2-b0 vf1-b7 vf1-b6 vf1-b5 vf1-b4 vf1-b3 vf1-b2 vf1-b1 vf1-b0 09h 08h 07h 06h 05h 04h 03h edh_flag 02h anc-ues anc-ida anc-idh anc-eda anc-edh ff-ues ff-ida ff-idh ff-eda ff-edh ap-ues ap-ida ap-idh ap-eda ap-edh 01h ioproc_disable 00h h_config 352m_ins illegal_re map edh_crc_in s anc_ csum_ins crc_ins lnum_ ins trs_ins
gs1531 data sheet 30573 - 4 july 2005 22 of 49 4. detailed description 4.1 functional overview the gs1531 is a multi-rate serializer with an integrated cable driver. when used in conjunction with the exter nal go1525 voltage controlle d oscillator, a transmit solution at 1.485gb/s, 1.485/1.001gb/s or 270mb/s is realized. the device has three different modes of operation which must be set by the application layer through external device pins. when smpte mode is enabled, the device w ill accept 10-bit multiplexed or 20-bit demultiplexed smpte compliant data at both hd and sd signal rates. the device?s additional processing features are also enabled in this mode. in dvb-asi mode, the gs1531 will accept an 8-bit parallel dvb-asi compliant transport stream on its upp er input bus. the serial output data stream will be 8b/10b encoded and stuffed. the gs1531?s third mode allows for the serializing of data not conforming to smpte or dvb-asi streams. the provided serial digital outputs feat ure a high impedance mode, output mute on loss of parallel clock and adjustable signal swing. the output slew rate is automatically controlled by the sd/hd setting. in the digital signal processing core, several data processing functions are implemented including smpte 352m and edh data packet generation and insertion, and automatic video standards de tection. these featur es are all enabled by default, but may be individually disabled via internal registers accessible through the gspi host interface. finally, the gs1531 contains a jtag interface for boundary scan test implementations. 4.2 parallel data inputs data inputs enter the device on the rising edge of pclk as shown in figure 4-1 . the input data format is defined by the setting of the external sd/hd , smpte_bypass and dvb_asi pins and may be presented in 10-bit or 20-bit format. the input data bus width is controlled independently from the internal data bus width by the 20bit/10bit input pin.
gs1531 data sheet 30573 - 4 july 2005 23 of 49 figure 4-1: pclk to data timing 4.2.1 parallel input in smpte mode when the device is operating in smpte mode, see smpte mode on page 25 , both sd and hd data may be presented to the input bus in either multiplexed or demultiplexed form depending on the setting of the 20bit/10bit input pin. in 20-bit mode, (20bit/10bit = high), the input data format should be word aligned, demultiplexed luma and chroma data. luma words should be presented to din[19:10] while chroma wo rds should occupy din[9:0]. in 10-bit mode, (20bit/10bit = low), the input data format should be word aligned, multiplexed luma and chroma data. the data should be presented to din[19:10]. din[9:0] will be high im pedance in this mode. 4.2.2 parallel input in dvb-asi mode when operating in dvb-asi mode, see dvb-asi mode on page 27 , the gs1531 automatically configures the input port for 10-bit operation regardless of the setting of the 20bit/10bit pin. the device will accept 8-bit data words on di n[17:10] such that din17 = hin is the most significant bit of the encoded transp ort stream data and din10 = ain is the least significant bit. in addition, din19 and din18 will be conf igured as the dvb-asi control signals inssyncin and kin respectively. see dvb-asi mode on page 27 for a description of these dvb-asi specific input signals. din[9:0] will be high impedan ce when the gs1 531 is operating in dvb-asi mode. 4.2.3 parallel input in data-through mode when operating in data-through mode, see data-through mode on page 28 , the gs1531 passes data presented to the parallel input bus to the serial output without performing any encoding or scrambling. the input data bus width acc epted by the device in this mode is controlled by the setting of the 20bit/10bit pin. pclk din[19:0] data control signal input t su t ih
gs1531 data sheet 30573 - 4 july 2005 24 of 49 4.2.4 parallel input clock (pclk) the frequency of the pclk input signal re quired by the gs1531 is determined by the input data format. table 4-1 below lists the possible input signal formats and their corresponding parallel clock rates. no te that dvb-asi inpu t will always be in 10-bit format, rega rdless of the setting of the 20bit/10bit pin. table 4-1: parallel data input format input data format din [19:10] din [9:0] pclk control signals 20bit/ 10bit sd/ hd smpte_bypass dvb_asi smpte mode 20bit demultiplexed sd luma chroma 13.5mhz high high high low 10bit multiplexed sd luma / chroma high impedance 27mhz low high high low 20bit demultiplexed hd luma chroma 74.25 or 74.25/ 1.001mhz high low high low 10bit multiplexed hd luma / chroma high impedance 148.5 or 148.5/ 1.001mhz low low high low dvb-asi mode 10bit dvb-asi dvb-asi data high impedance 27mhz high high low high low high low high data-through mode 20bit demultiplexed sd data data 13.5mhz high high low low 10bit multiplexed sd data high impedance 27mhz low high low low 20bit demultiplexed hd data data 74.25 or 74.25/ 1.001mhz high low low low 10bit multiplexed hd data high impedance 148.5 or 148.5/ 1.001mhz low low low low
gs1531 data sheet 30573 - 4 july 2005 25 of 49 4.3 smpte mode the gs1531 is said to be in smpte mode when the smpte_bypass pin is set high and the dvb_asi pin is set low. in this mode, the parallel data will be scrambled acco rding to smpte 259m or 292m, and nrz-to-nrzi encoded prior to serialization. 4.3.1 internal flywheel the gs1531 has an internal flywheel which is used in the generation of internal / external timing signals, and in autom atic video standards detection. it is operational in smpte mode only. the flywheel consists of a number of coun ters and comparators operating at video pixel and video line rates. these counters maintain information about the total line length, active line length, total number of lin es per field / frame and total active lines per field / frame for the received video standard. when detect_trs is low, the flywheel will be locked to the externally supplied h, v, and f timing signals. when detect_trs is high, the flywheel will be locked to the embedded trs signals in the para llel input data. both 8-bit and 10-bit trs code words will be identified by the device. the flywheel 'learns' the video standard by timing the horizontal and vertical reference information supplied a the h, v, and f input pins, or contained in the trs id words of the received video data. full synchronization of the flywheel to the received video standard therefore requires one complete video frame. once synchronization has be en achieved, the fl ywheel will continue to monitor the received trs timing or the supplied h, v, and f timing information to maintain synchronization. 4.3.2 hvf timing signal extraction as discussed above, the gs1531's internal flywheel may be locked to externally provided h, v, and f signals when detect_trs is set low by the application layer. the h signal timing should also be configured via the h_config bit of the internal ioproc_disable register as either ac tive line based blanking or trs based blanking, see packet generation and insertion on page 30 . active line based blanking is enabled when the h_config bit is set low. in this mode, the h input should be high for the entire horizontal blanking period, including the eav and sav trs words. this is the default h timing assumed by the device. when h_config is se t high, trs based blanking is enabled. in this case, the h input should be set high for the entire ho rizontal blanking period as indicated by the h bit in the associated trs words.
gs1531 data sheet 30573 - 4 july 2005 26 of 49 the timing of these signals is shown in figure 4-2 . figure 4-2: h, v, f timing h:v:f timing - hd 20-bit input mode pclk luma data out chroma data out h xyz (eav) 000 000 3ff xyz (eav) 000 000 3ff v f xyz (sav) 000 000 3ff xyz (sav) 000 000 3ff h;v:f timing at sav - hd 10-bit input mode 000 000 3ff 3ff xyz (sav) 000 000 xyz (sav) pclk h v f h:v:f timing at eav - hd 10-bit input mode pclk 000 000 3ff 3ff xyz (eav) 000 000 xyz (eav) multiplexed y/cr/cb data out h v f multiplexed y/cr/cb data out h:v:f timing - sd 20-bit input mode pclk chroma data out luma data out h 000 3ff xyz (eav) 000 v f 000 3ff xyz (sav) 000 h:v:f timing - sd 10-bit input mode multiplexed y/cr/cb data out pclk h v f xyz (eav) 000 000 3ff xyz (sav) 000 000 3ff h signal timing: h_config = low h_config = high
gs1531 data sheet 30573 - 4 july 2005 27 of 49 4.4 dvb-asi mode the gs1531 is said to be in dvb-asi mode wh en the smpte_bypass pin is set low and the dvb_asi and sd/hd pins are set high. in this mode, all smpte processing functions are disabled, and the 8-bit transport stream data will be 8b/10b enco ded prior to serialization. 4.4.1 control signal inputs in dvb-asi mode, the din19 and din 18 pins will be configured as dvb-asi control signals inssyncin and kin respectively. when inssyncin is set high, the device w ill insert k28.5 sync characters into the data stream. this function is used to assist system implementations where the gs1531 may be preceded by an extern al data fifo. parallel dvb-asi data may be clocked into the fifo at some ra te less than 27mhz. the inssyncin input may then be connected to the fifo empt y signal, thus providing a means of padding up the data transmission rate to 27mhz. see figure 4-3 . note: 8b/10b encoding will take place after k28.5 sync character insertion. kin should be set high whenever the paralle l data input is to be interpreted as any special character defined by the dvb- asi standard (including the k28.5 sync character). this pin should be set low when the input is to be interpreted as data. note: when operating in dvb-asi mode, din[9:0] become high impedance. figure 4-3: dvb-asi fifo impl ementation using the gs1531 8 8 ain ~ hin pclk = 27mhz inssyncin sdo clk_in clk_out fifo sdo write_clk <27mhz fe ts kin gs1531 kin read clk =27mhz
gs1531 data sheet 30573 - 4 july 2005 28 of 49 4.5 data-through mode the gs1531 may be configured by the application layer to operate as a simple parallel-to-serial converter. in this mode, the device presents data to the output buffer without performing any scrambling or encoding. data-through mode is enabled only when both the smpte_bypass and dvb_asi pins are set low. 4.6 additional processing functions the gs1531 contains an additional data processing block which is available in smpte mode only, see smpte mode on page 25 . 4.6.1 input data blank the video input data may be 'blanked' by th e gs1531. in this mode, all input video data except trs words are set to the appr opriate blanking levels by the device. both the horizontal and vertical ancillary data spaces will also be set to blanking levels. this function is enabled by setting the blank pin low. 4.6.2 automatic video standard detection the gs1531 can detect the input video standard by using the timing parameters extracted from the received trs id words or supplied h, v, and f timing signals, see internal flywheel on page 25 . this information is presented to the host interface via the video_standard register ( table 4-2 ). total samples per line, active samples per line, total lines per field/frame and active lines per field/frame are also calculated an d presented to the host interface via the raster_structure registers ( table 4-3 ). these line and sample count registers are updated once per frame at the end of line 12. this is in addition to the information contained in th e video_standard register. after device reset, the four raster_s tructure registers default to zero. table 4-2: host interface description for video standard register register name bit name description r/w default video_standard address: 004h 15 ? not used. ? ? 14-10 vd_std[4:0] video data standard (see table 4-4 ). r 0 9 int_prog interlace/progressive: set low if detected video standard is progressive and is set high if it is interlaced. r0 8 std_lock standard lock: set high when flywheel has achieved full synchronization. r0 7-0 ? not used. ? ?
gs1531 data sheet 30573 - 4 july 2005 29 of 49 4.6.2.1 video standard indication the video standard codes reported in the vd_std[4:0] bits of the video_standard register represent the smpte standards as shown in table 4-4 . in addition to the 5-bit video standard code word, the video_standard register also contains two status bits. the std_ lock bit will be set high whenever the flywheel has achieved full sy nchronization. the int_prog bit will be set high if the detected video standard is progressiv e and low if the dete cted video standard is interlaced. the vd_std[4:0], std_lock and int_prog bits of the video_standard register will default to zero after devi ce reset. the vd_std[4:0] and int_prog bits will also default to zero if the smpte_bypass pin is asserted low or if the locked output is low. the std_lock bi t will retain its previous value if the pclk is removed. table 4-3: host interface descript ion for raster structure registers register name bit name description r/w default raster_structure1 address: 00eh 15-12 ? not used. ? ? 11-0 raster_structure_1[11:0] words per active line r 0 raster_structure2 address: 00fh 15-12 ? not used. ? ? 11-0 raster_structure_2[11:0] words per total line. r 0 raster_structure3 address: 010h 15-11 ? not used. ? ? 10-0 raster_structure_3[10:0] total lines per frame r 0 raster_structure4 address: 011h 15-11 ? not used. ? ? 10-0 raster_structure_4[10:0] active lines per field r 0 table 4-4: supported video standards vd_std[4:0] smpte standard video format length of hanc length of active video total samples smpte352m lines 00h 296m (hd) 1280x720/60 (1:1) 358 1280 1650 13 01h 296m (hd) 1280x720/60 (1:1) - em 198 1440 1650 13 02h 296m (hd) 1280x720/30 (1:1) 2008 1280 3300 13 03h 296m (hd) 1280x720/30 (1:1) - em 408 2880 3300 13 04h 296m (hd) 1280x720/50 (1:1) 688 1280 1980 13 05h 296m (hd) 1280x720/50 (1:1) - em 240 1728 1980 13 06h 296m (hd) 1280x720/25 (1:1) 2668 1280 3960 13 07h 296m (hd) 1280x720/25 (1:1) - em 492 3456 3960 13
gs1531 data sheet 30573 - 4 july 2005 30 of 49 4.6.3 packet generati on and insertion in addition to input data blanking and automatic vi deo standards detection, the gs1531 may also calculate, assemble an d insert into the da ta stream various types of ancillary data packets and trs id words. 08h 296m (hd) 1280x720/24 (1:1) 2833 1280 4125 13 09h 296m (hd) 1280x720/24 (1:1) - em 513 3600 4125 13 0ah 274m (hd) 1920x1080/60 (2:1) or 1920x1080/30 (psf) 268 1920 2200 10, 572 0bh 274m (hd) 1920x1080/30 (1:1) 268 1920 2200 18 0ch 274m (hd) 1920x1080/50 (2:1) or 1920x1080/25 (psf) 708 1920 2640 10, 572 0dh 274m (hd) 1920x1080/25 (1:1) 708 1920 2640 18 0eh 274m (hd) 1920x1080/25 (1:1) - em 324 2304 2640 18 0fh 274m (hd) 1920x1080/25 (psf) - em 324 2304 2640 10, 572 10h 274m (hd) 1920x1080/24 (1:1) 818 1920 2750 18 11h 274m (hd) 1920x1080/24 (psf) 818 1920 2750 10, 572 12h 274m (hd) 1920x1080/24 (1:1) - em 338 2400 2750 18 13h 274m (hd) 1920x1080/24 (psf) - em 338 2400 2750 10, 572 14h 295m (hd) 1920x1080/50 (2:1) 444 1920 2376 10, 572 15h 260m (hd) 1920x1035/60 (2:1) 268 1920 2200 10, 572 16h 125m (sd) 1440x487/60 (2:1) (or dual link progressive) 268 1440 1716 13, 276 17h 125m (sd) 1440x507/60 (2:1) 268 1440 1716 13, 276 19h 125m (sd) 525-line 487 generic ? ? 1716 13, 276 1bh 125m (sd) 525-line 507 generic ? ? 1716 13, 276 18h itu-r bt.656 (sd) 1440x576/50 (2:1) (or dual link progressive) 280 1440 1728 9, 322 1ah itu-r bt.656 (sd) 625-line generic (em) ? ? 1728 9, 322 1dh unknown hd ? ? ? ? ? 1eh unknown sd ? ? ? ? ? 1ch, 1fh reserved ? ? ? ? ? note: though the gs1531 will work correctly on and serialize both 59.94hz and 60hz formats, it will not distinguish between the m. table 4-4: supported video standards (continued) vd_std[4:0] smpte standard video format length of hanc length of active video total samples smpte352m lines
gs1531 data sheet 30573 - 4 july 2005 31 of 49 these features are only available when th e device is set to operated in smpte mode and the ioproc_en/dis pin is set high. individual insertion features may be enabled or disabled via the ioproc_disable register ( table 4-5 ). all of the ioproc_disable register bits de fault to '0' after device reset, enabling all of the processing features. to disable any individual error correction feature, the host interface must set the corresponding bit high in this register. table 4-5: host interface description fo r internal processing disable register register name bit name description r/w default ioproc_disable address: 000h 15-9 ? not used. ? ? 8 h_config horizontal sync timing input configuration. set low when the h input timing is based on active line blanking (default). set high when the h input timing is based on the h bit of the trs words. see figure 4-2 . r/w 0 7 ? not used. ? ? 6 352m_ins smpte352m packet insertion. in hd mode, 352m packets are inserted in the y channel only when the four video_format_in registers are programmed with non-zero values. the ioproc_en/dis pin and smpte_bypass pin must also be set high. set high to disable. r/w 0 5 illegal_remap illegal code remapping. detection and correction of illegal code words within the active picture area (ap). the ioproc_en/dis pin and smpte_bypass pin must also be set high. set high to disable. r/w 0 4 edh_crc_ins error detection & handling (edh) cyclical redundancy check (crc) error correction. in sd mode the gs1531 will generate and insert edh packets. the ioproc_en/dis pin and smpte_bypass pin must also be set high. set high to disable. r/w 0 3 anc_csum_ins ancillary data checksum insertion. the ioproc_en/dis pin and smpte_bypass pin must also be set high. set high to disable. r/w 0 2 crc_ins y and c line-based crc insertion. in hd mode, line-based crc words are inserted in both the y and c channels. the ioproc_en/dis pin and smpte_bypass pin must be also set high. set high to disable r/w 0 1 lnum_ins y and c line number insertion - hd mode only. the ioproc_en/dis pin and smpte_bypass pin must be set high. set high to disable. r/w 0 0 trs_ins timing reference signal insertion. occurs only when ioproc_en/dis is high and smpte_bypass is high. set high to disable. r/w 0
gs1531 data sheet 30573 - 4 july 2005 32 of 49 4.6.3.1 smpte 352m payloa d identifier insertion the gs1531 can generate and insert smpte 352m payl oad identifier ancillary data packets into the data stream, based on information programmed into the host interface. when this feature is enabl ed, the device will automatica lly generate the ancillary data preambles, (did, sdid, dbn, dc), and calculate the checksum. the smpte 352m packet will be inserted into the dat a stream according to the line numbers programmed in the line_352m registers ( table 4-6 ). the insertion process will only take pl ace if one or more of the four video_format registers ( table 4-7 ) have been programmed with non-zero values. in addition, the gs1531 requires the 352m_ins bit of the ioproc_disable register be set low. note 1: for the purpose of determining the line and pixel position for insertion, the gs1531 will differentiate between psf and in terlaced formats by interrogating bits 14 and 15 of the video_format_a register. the packets will be inse rted immediately after the eav word in sd video streams and immediately after the line-based crc word in the y channel of hd video streams. note 2: it is the responsib ility of the user to ensure th at there is sufficient space in the horizontal blanking interval for the insertion of the smpte 352m packets. if there are other ancillary data pa ckets present, the sm pte 352m packet will be inserted in the first available location in the horizontal ancilla ry space. ancillary data must be adjacent to the eav in sd streams or to the line based-crc in hd streams. where there is insufficient spac e available, the 352m packets will not be inserted. table 4-6: host interface description for smpte 352m packet line number insertion registers register name bit name description r/w default line_352m_f1 address: 01bh 15-11 ? not used. ? ? 10-0 line_0_352m[10:0] line number where smpte352m packet is inserted in field 1. r/w 0 line_352m_f2 address: 01ch 15-11 ? not used. ? ? 10-0 line_1_352m[10:0] line number where smpte352m packet is inserted in field 2. r/w 0
gs1531 data sheet 30573 - 4 july 2005 33 of 49 4.6.3.2 illegal code remapping if the illegal_remap bit of the iopr oc_disable register is set low, the gs1531 will remap all codes within the acti ve picture between the values of 3fch and 3ffh to 3fbh. all codes within the ac tive picture area between the values of 000h and 003h will be remapped to 004h. in addition, 8-bit trs and ancillary data preambles will be remapped to 10-bit values if this feature is enabled. 4.6.3.3 edh generation and insertion when operating in sd mode, (sd/hd = high), the gs1531 will generate and insert complete edh packets into the data stream. packet generation and insertion will only take place if the edh_crc_ins bi t of the ioproc_disable register is set low. the gs1531 will g enerate all of t he required edh packet data including all ancillary data preambles, (did, dbn, dc), reserved code words and checksum. calculation of both full field (ff) and active picture (ap) crc's will be carried out by the device. smpte rp165 specifies the calculation ranges and scope of edh data for standard 525 and 625 component digita l interfaces. the gs1531 will utilize these standard ranges by default. if the received video format does not correspond to 525 or 625 digital component video standards as determined by the flywheel pixel and line counters, then one of two schemes for determining the edh calculation ranges will be employed: 1. ranges will be based on the line and pixel ranges programmed by the host interface; or 2. in the absence of us er-programmed ca lculation ranges, ranges will be determined from the received trs id words or supplied h, v, and f timing signals, see internal flywheel on page 25 . table 4-7: host interface description for smpte 352m payload identifier registers register name bit name description r/w default video_format_b address: 00bh 15-8 smpte352m byte 4 smpte 352m byte 4 information must be programmed in this register when 352m_ins = low. r/w 0 7-0 smpte352m byte 3 smpte 352m byte 3 information must be programmed in this register when 352m_ins = low. r/w 0 video_format_a address: 00ah 15-8 smpte352m byte 2 smpte 352m byte 2 information must be programmed in this register when 352m_ins = low. r/w 0 7-0 smpte 352m byte 1 smpte 352m byte 1 information must be programmed in this register when 352m_ins = low. r/w 0
gs1531 data sheet 30573 - 4 july 2005 34 of 49 the registers available to the host interface for programming edh calculation ranges include active picture and full fi eld line start and end positions for both fields. table 4-8 shows the relevant registers, which default to '0' after device reset. if any or all of these register values are zero, then the edh crc calculation ranges will be determined from the flywheel genera ted h signal. the first active and full field pixel will always be the first pixel afte r the sav trs code word. the last active and full field pixel will always be the last pixel before the star t of the eav trs code words. edh error flags (edh, eda, idh, ida and ues) for ancillary data, full field and active picture will also be inserted. these flags must be programmed into the edh_flag registers of the device by the application layer ( table 4-9 ). note 1: it is the responsibilit y of the user to ensure that the edh flag registers are updated once per field. the prepared edh packet will be inserted at the appropriate line of the video stream according to rp165. the start pixel position of the inserted packet will be based on the sav position of that line such that the last byte of the edh packet (the checksum) will be placed in the sample immediately preceding the start of the sav trs word. note 2: it is also the responsibility of th e user to ensure that there is sufficient space in the horizontal blanking interval for the edh packet to be inserted. table 4-8: host interface description for edh calculation range registers register name bit name description r/w default ap_line_start_f0 address: 012h 15-10 ? not used. ? ? 9-0 ap_line_start_f0[9:0] field 0 active picture start line data used to set edh calculation range outside of rp 165 values. r/w 0 ap_line_end_f0 address: 013h 15-10 ? not used. ? ? 9-0 ap_line_end_f0[9:0] field 0 active picture end line data used to set edh calculation range outside of rp 165 values. r/w 0 ap_line_start_f1 address: 014h 15-10 ? not used. ? ? 9-0 ap_line_start_f1[9:0] field 1 active picture start line data used to set edh calculation range outside of rp 165 values. r/w 0 ap_line_end_f1 address: 015h 15-10 ? not used. ? ? 9-0 ap_line_end_f1[9:0] field 1 active picture end line data used to set edh calculation range outside of rp 165 values. r/w 0
gs1531 data sheet 30573 - 4 july 2005 35 of 49 ff_line_start_f0 address: 016h 15-10 ? not used. ? ? 9-0 ff_line_start_f0[9:0] field 0 full field start line data used to set edh calculation range outside of rp 165 values. r/w 0 ff_line_end_f0 address: 017h 15-10 ? not used. ? ? 9-0 ff_line_end_f0[9:0] field 0 full field end line data used to set edh calculation range outside of rp 165 values. r/w 0 ff_line_start_f1 address: 018h 15-10 ? not used. ? ? 9-0 ff_line_start_f1[9:0] field 1 full field start line data used to set edh calculation range outside of rp-165 values. r/w 0 ff_line_end_f1 address: 019h 15-10 ? not used. ? ? 9-0 ff_line_end_f1[9:0] field 1 full field end line data used to set edh calculation range outside of rp-165 values. r/w 0 table 4-8: host interface description for ed h calculation range registers (continued) register name bit name description r/w default table 4-9: host interface description for edh flag register register name bit name description r/w default edh_flag address: 002h 15 ? not used. ? ? 14 anc-ues ancillary unknown error status flag will be generated and inserted when ioproc_en/dis and smpte_bypass pins are high and edh_crc_ins bit is low. sd mode only. r/w 0 13 anc-ida ancillary internal device error detected already flag will be generated and inserted when ioproc_en/dis and smpte_bypass pins are high and edh_crc_ins bit is low. sd mode only. r/w 0 12 anc-idh ancillary internal device error detected here flag will be generated and inserted when ioproc_en/dis and smpte_bypass pins are high and edh_crc_ins bit is low. sd mode only. r/w 0 11 anc-eda ancillary error de tected already flag will be generated and inserted when ioproc_en/dis and smpte_bypass pins are high and edh_crc_ins bit is low. sd mode only. r/w 0 10 anc-edh ancillary error detected here flag will be generated and inserted when ioproc_en/dis and smpte_bypass pins are high and edh_crc_ins bit is low. sd mode only. r/w 0
gs1531 data sheet 30573 - 4 july 2005 36 of 49 9 ff-ues full field unknown error flag will be generated and inserted when ioproc_en/dis and smpte_bypass pins are high and edh_crc_ins bit is low. sd mode only. r/w 0 8 ff-ida full field internal device error detected already flag will be generated and inserted when ioproc_en/dis and smpte_bypass pins are high and edh_crc_ins bit is low. sd mode only. r/w 0 7 ff-idh full field internal device error detected flag will be generated and inserted when ioproc_en/dis and smpte_bypass pins are high and edh_crc_ins bit is low. sd mode only. r/w 0 6 ff-eda full field error detected already flag will be generated and inserted when ioproc_en/dis and smpte_bypass pins are high and edh_crc_ins bit is low. sd mode only. r/w 0 5 ff-edh full field error detected here flag will be generated and inserted when ioproc_en/dis and smpte_bypass pins are high and edh_crc_ins bit is low. sd mode only. r/w 0 4 ap-ues active picture unknown error status flag will be generated and inserted when ioproc_en/dis and smpte_bypass pins are high and edh_crc_ins bit is low. sd mode only. r/w 0 3 ap-ida active picture internal device error detected already flag will be generated and inserted when ioproc_en/dis and smpte_bypass pins are high and edh_crc_ins bit is low. sd mode only. r/w 0 2 ap-idh active picture internal device error detected here flag will be generated and inserted when ioproc_en/dis and smpte_bypass pins are high and edh_crc_ins bit is low. sd mode only. r/w 0 1 ap-eda active picture error detected already flag will be generated and inserted when ioproc_en/dis and smpte_bypass pins are high and edh_crc_ins bit is low. sd mode only. r/w 0 0 ap-edh active picture error detected here flag will be generated and inserted when ioproc_en/dis and smpte_bypass pins are high and edh_crc_ins bit is low. sd mode only. r/w 0 table 4-9: host interface description for edh flag register (continued) register name bit name description r/w default
gs1531 data sheet 30573 - 4 july 2005 37 of 49 4.6.3.4 ancillary data checks um generation and insertion the gs1531 will calculate ch ecksums for all detected ancillary data packets presented to the device. these calculated checksum values are inserted into the data stream prior to serialization. ancillary data checksum generation and insertion will only take place if the anc_csum_ins bit of the iopro c_disable register is set low. 4.6.3.5 line based crc ge neration and insertion the gs1531 will generat e and insert line based crc wo rds into both the y and c channels of the data stream. this featur e is only available in hd mode and is enabled by setting the crc_ins bit of the iopr oc_disable register low. 4.6.3.6 hd line number generation and insertion in hd mode, the gs1531 will calculate a nd insert line numbers into the y and c channels of the output data stream. line number generation is in accordance with the relevant hd video standard as determined by the device, see automatic video standard detection on page 28 . this feature is enabled when sd/hd = low, and the lnum_ins bit of the ioproc_disable register is set low. 4.6.3.7 trs generation and insertion the gs1531 can generate and insert 10-bit trs code words into the data stream as required. this feature is enabled by setting the trs_ins bit of the ioproc_disable register low. trs word generation will be performed in accord ance with the timing parameters generated by the flyw heel which will be locked either to the received trs id words or the supplied h, v, and f timing signals, see internal flywheel on page 25 . 4.7 parallel-to-serial conversion the parallel data output of the internal data processing blocks is fed to the parallel-to-serial converter. the function of this block is to generate a serial data stream from the 10-bit or 20-bit parallel data words and pass the stream to the integrated cable driver.
gs1531 data sheet 30573 - 4 july 2005 38 of 49 4.8 serial digital data pll to obtain a clean clock signal for serializ ation and transmission, the input pclk is locked to an external reference signal via the gs1531's integrated phase-locked loop. this high quality analog pll allows the gs1531 to significantly attenuate jitter on the incoming pclk. this pll is also responsible for generating all internal clock signals required by the device. internal division ratios for the locked pclk are determined by the setting of the sd/hd and 20bit/10bit pins as shown in table 4-10 . 4.8.1 external vco the gs1531 requir es the go1525 external voltage controlled oscillator as part of its internal pll. power for the external vco is generated entirely by the gs1531 from an integrated voltage regulator. the internal regulator uses +3.3v supplied on the cp_vdd / cp_gnd pins to provide +2.5v on the vco_vcc / vco_gnd pins. the external vco produces a 1.485ghz reference signal for the pll, input on the vco pin of the device. both reference and control signals should be referenced to the supplied vco_gnd as shown in the recommended application circuit of typical application circuit on page 45 . 4.8.2 lock detect output the lock detect block controls the serial digital output signal and indicates to the application layer the lock status of the device via the locked output pin. locked will be asserted high if and only if the internal data pll has locked the pclk signal to the external vco referenc e signal and one of the following is true: 1. the device is set to operate in smpte mode and has detected smpte trs words in the serial stream; or 2. the device is set to operate in dvb-asi mode and has detected k28.5 sync characters in the serial stream; or 3. the device is set to operate in data-through mode. table 4-10: serial digital output rates supplied pclk rate serial digital output rate pin settings sd/hd 20bit/10bit 74.25 or 74.25/1.001 mhz 1.485 or 1.485/1.001gb/s low high 148.5 or 148.5/1.001mhz 1.485 or 1.485/1.001gb/s low low 13.5mhz 270mb/s high high 27mhz 270mb/s high low
gs1531 data sheet 30573 - 4 july 2005 39 of 49 4.9 serial digital output the gs1531 contains an integrated current mode differential serial digital cable driver with automatic slew rate control. the integrated cable driver uses a separate power supply of +1.8v dc supplied via the cd_vdd and cd_gnd pins. to enable the output, sdo_en/dis must be set high by the application layer. setting the sdo_en/dis signal low will cause the sdo and sdo output pins to become high impedance, resulting in reduced device power consumption. gennum recommends using the gs1528a sd i dual slew-rate cable driver to meet smpte specifications. 4.9.1 output swing nominally, the voltage swing of the serial digital output is 800mvp-p single-ended into a 75 load. this is set exte rnally by connecting the rset pin to cd_vdd through 281 . the output swing may be decreased by increasing the value of the rset resistor. the relationship is approximated by the curve shown in figure 4-4 . alternatively, the serial digital outpu t swing can drive 800mvp-p into a 50 load. since the output swing is reduced by a factor of approximately one third when the smaller load is used, the rset resistor must be 187 to obtain 800mvp-p. figure 4-4: serial digi tal output swing 4.9.2 serial digital output mute the gs1531 will automa tically mute the serial digi tal output when the locked output signal is low. in this case, the sdo and sdo signals are set to a constant voltage level. 50 load 300 400 500 600 700 800 900 1000 250 300 350 400 450 500 550 600 650 700 rset( ) v sdo (mvp-p) 200 75 load
gs1531 data sheet 30573 - 4 july 2005 40 of 49 4.10 gspi host interface the gspi, or gennum serial peripheral interface, is a 4-wire interface provided to allow the host to enable additional features of the device and /or to provide additional status information through configuration registers in the gs1531. the gspi comprises a serial data inpu t signal sdin, serial data output signal sdout, an active low chip select cs , and a burst clock sclk. the burst clock must have a duty cycle between 40% and 60%. because these pins are shared with the jtag interface port, an additional control signal pin jtag/host is provided. when jtag/host is low, the gspi interface is enabled. when operating in gspi mode, the sclk, sdin, and cs signals are provided by the host interface. the sdout pin is a high-impedance output allowing multiple devices to be connected in parallel and selected via the cs input. the interface is illustrated in the figure 4-5 below. all read or write access to the gs1531 is initiated and terminated by the host processor. each access always begins with a 16-bit command word on sdin indicating the address of the register of interest. this is followed by a 16-bit data word on sdin in write mode, or a 16-bit data word on sdout in read mode. figure 4-5: gennum serial peripheral interface (gspi) 4.10.1 command word description the command word is transmitted msb firs t and contains a read/write bit, nine reserved bits and a 6-bit register address. set r/w = '1' to read and r/w = '0' to write from the gspi. command words are clocked into the gs1531 on the rising edge of the serial clock sclk. the appropriate chip select signal, cs , must be asserted low a minimum of 1.5ns (t0 in figure 4-8 and figure 4-9 ) before the first clock edge to ensure proper operation. each command word must be followed by only one data word to ensure proper operation. sclk cs sdout sdin sclk cs sdin sdout application host gs1531
gs1531 data sheet 30573 - 4 july 2005 41 of 49 figure 4-6: command word figure 4-7: data word 4.10.2 data read and write timing read and write mode timing for the gspi interface is shown in figure 4-8 and figure 4-9 respectively. the maximum sclk frequency allowed is 6.6mhz. when writing to the regist ers via the gspi, the msb of the data word may be presented to sdin immediately followin g the falling edge of the lsb of the command word. all sdin data is sampled on the rising edge of sclk. when reading from the regi sters via the gspi, the msb of the data word will be available on sdout 12ns (t5) following t he falling edge of the lsb of the command word, and thus may be read by the host on the very next rising edge of the clock. the remaining bits are clocked out by th e gs1531 on the negative edges of sclk. figure 4-8: gspi read mode timing figure 4-9: gspi write mode timing r/w rsv rsv rsv a0 a1 a2 a3 a4 a5 rsv rsv rsv rsv rsv rsv msb lsb d15 d14 d13 d12 d0 d1 d2 d3 d4 d5 d6 d7 d8 d9 d11 d10 msb lsb sdout r/w rsv rsv a0 a1 a2 a3 a4 a5 rsv rsv rsv rsv rsv rsv d15 d14 d13 d12 d0 d1 d2 d3 d4 d5 d6 d7 d8 d9 d11 d10 sclk cs sdin rsv t 0 t 2 t 3 input data setup time duty cycle t 4 period t 5 t 6 output data hold time r/w rsv rsv a0 a1 a2 a3 a4 a5 rsv rsv rsv rsv rsv rsv d15 d14 d13 d12 d0 d1 d2 d3 d4 d5 d6 d7 d8 d9 d11 d10 sclk cs sdin rsv t 0 t 2 t 3 input data setup time duty cycle t 4 period
gs1531 data sheet 30573 - 4 july 2005 42 of 49 4.10.3 configuration and status registers table 4-11 summarizes the gs1531's internal st atus and configuration registers. all of these registers are available to the host via the gspi and are all individually addressable. where status registers contain less than th e full 16 bits of information however, two or more registers may be combined at a single logical address. 4.11 jtag when the jtag/host input pin of the gs1531 is se t high, the host interface port will be configured for jtag test operation. in this mode , pins h4 to h6 and j6 become tms, tck, tdo, and tdi. in addition, the reset_trst pin will operate as the test reset pin. boundary scan testing using the jtag interface will be enabl ed in this mode. there are two methods in which jtag can be used on the gs1531: 1. as a stand-alone jtag interface to be used at in-circuit ate (automatic test equipment) during pcb assembly; or 2. under control of the host for applications such as system power on self tests. when the jtag tests are applied by ate, care must be taken to disable any other devices driving the digital i/o pins. if the te sts are to be applied only at ate, this can be accomplished with tri-state bu ffers used in conjunction with the jtag/host input signal. this is shown in figure 4-10 . table 4-11: gs1531 internal registers address register name see section 000h ioproc_disable section 4.6.3 002h edh_flag section 4.6.3.3 004h video_standard section 4.6.2 010h - 011h video_format section 4.6.3.1 014h - 017h raster_structure section 4.6.2 018h - 025h edh_calc_ranges section 4.6.3.3 027h - 028h line_352m section 4.6.3.1
gs1531 data sheet 30573 - 4 july 2005 43 of 49 figure 4-10: in-circuit jtag alternatively, if the test ca pabilities are to be used in the system, the host may still control the jtag/host input signal, but some means for tri-stating the host must exist in order to use the interface at ate. this is represented in figure 4-11 . figure 4-11: system jtag please contact your gennum representat ive to obtain the bsdl model for the gs1531. application host gs1531 cs_tms sclk_tck sdin_tdi sdout_tdo jtag_host in-circuit ate probe application host gs1531 cs_tms sclk_tck sdin_tdi sdout_tdo jtag_host in-circuit ate probe tri-state
gs1531 data sheet 30573 - 4 july 2005 44 of 49 4.12 device power up the gs1531 has a recommended power supply sequence. to ensure correct power up, power the core_vdd pins before the io_vdd pins. device pins may also be driven prio r to power up without causing damage. to ensure that all internal registers are cleared upon power-up, the application layer must hold the reset_trst signal low for a minimum of 1ms after the core power supply has reached the minimum le vel specified in the dc electrical characteristics table, table 2-1 . see figure 4-12 . 4.13 device reset in order to initialize all in ternal operating conditions to their default states the application layer must hold the reset_trst signal low for a minimum of t reset = 1ms. when held in reset, all device outputs will be driven to a high-impedance state. figure 4-12: reset pulse core_vdd reset_trst t reset +1.65v +1.8v reset reset t reset
gs1531 data sheet 30573 - 4 july 2005 45 of 49 5. application reference design 5.1 typical application circuit gs1531 vco_gnd vco_vcc a2 a3 vco vco lf a5 a4 a1 cp_cap lb_cont vco_vcc 1u 10n gnd_vco vco_vcc go1525 5 4 8 2 7 1 3 6 vctr gnd gnd gnd vcc o/p nc gnd 10n 10n gnd_vco gnd_vco gnd_vco gnd_vco gnd_vco 100n 0 gnd_vco gnd_vco b1 b4 +3.3v cp_vdd cp_gnd 0 1u 1u 10n 10n 0 gnd_a +1.8v_a 10n gnd_a din18 din19 data[19..0] data18 data19 a9 a10 data0 data1 din1 din0 k10 k9 data12 data13 data14 data16 data17 data15 din13 din12 din14 din15 din16 din17 data11 data10 data9 din9 din10 din11 f10 data7 data8 data3 data6 data2 data4 data5 din2 din3 din4 din5 din6 din7 din8 j10 j9 h10 h9 g10 g9 f9 e9 e10 d9 d10 c9 c10 b9 b10 a6 b5 b6 c4 c5 d2 d3 d7 e3 e7 f2 f7 f3 g2 g7 g3 h3 j2 j4 j3 e2 rsv f1 d1 e1 h2 j1 g1 h1 rset +1.8v_a 281 +/-1% 10n k1 b7 c7 c6 d5 d4 e4 f4 g4 g5 j5 k6 h4 h6 j6 h5 g6 reset_trst jtag/host dvb_asi smpte_bypass sd/hd sclk_tck sdout_tdo sdin_tdi cs_tms 20bit/10bit ioproc_en/dis sdo_en/dis jtag/host dvb_asi reset_trst 20bit/10bit ioproc_en/dis sdo_en/dis jtag/host dvb_asi smpte_bypass sd/hd sclk_tck sdout_tdo sdin_tdi cs_tms c8 d8 d6 h7 g8 k7 j7 h8 locked f v h a7 pclk pclk lock blank f v h core_vdd core_gnd e6 e5 core_gnd core_vdd f5 f6 io_gnd io_vdd j8 k8 io_gnd io_vdd f8 e8 io_vdd io_gnd a8 b8 sdo sdo +1.8v_a 50 50 10n gnd_a k3 k4 cd_vdd cd_gnd k2 k5 cp_vdd cp_gnd b3 b2 pd_gnd pd_vdd c3 c2 c1 core_vdd core_gnd core_gnd core_vdd io_gnd io_vdd io_gnd io_vdd io_vdd io_gnd cp_vdd cp_gnd pd_gnd pd_vdd +3.3v io_gnd io_vdd 1u 10n gnd_d +3.3v io_gnd io_vdd 1u 10n gnd_d +3.3v io_gnd io_vdd 1u 10n gnd_d +1.8v core_gnd core_vdd 10n gnd_d +1.8v core_gnd core_vdd 10n gnd_d pd_gnd pd_vdd +1.8v 10n gnd_a gnd_a blank 75 pclk lock f v h pclk lock blank f v h blank reset_trst sclk_tck sdout_tdo sdin_tdi 20bit/10bit ioproc_en/dis sdo_en/dis detect_trs jtag/host dvb_asi note: smpte_bypass, sd/hd, dvb_asi, and rc_byp are inputs in slave mode (master/slave = low), and are outputs in master mode (master/slave = high). smpte_bypass sd/hd reset_trst sclk_tck sdout_tdo sdin_tdi 20bit/10bit ioproc_en/dis sdo_en/dis jtag/host dvb_asi smpte_bypass sd/hd cs_tms cs_tms detect_trs detect_trs detect_trs r 2 vco_vcc do not populate r 2 22n 50 to the gs1528a cable driver note: see gennum's reference design: "interfacing the gs1532 to the gs1528 multi-rate cable driver"
gs1531 data sheet 30573 - 4 july 2005 46 of 49 6. references & relevant standards smpte 125m component video signal 4:2:2 ? bit parallel interface smpte 260m 1125 / 60 high definition producti on system ? digital representation and bit parallel interface smpte 267m bit parallel digital interface ? co mponent video signal 4:2:2 16 x 9 aspect ratio smpte 274m 1920 x 1080 scanning analog and parallel digi tal interfaces for multiple picture rates smpte 291m ancillary data packet and space formatting smpte 292m bit-serial digital interface for high-definition television systems smpte 293m 720 x 483 active line at 59.94 hz progressive scan production ? digital representation smpte 296m 1280 x 720 scanning, analog and digita l representation and analog interface smpte 352m video payload identification for digital television interfaces smpte rp165 error detection checkwords and st atus flags for use in bit-serial digital interfaces for television smpte rp168 definition of vertical interval sw itching point for synchronous video switching
gs1531 data sheet 30573 - 4 july 2005 47 of 49 7. package & ordering information 7.1 package dimensions
gs1531 data sheet 30573 - 4 july 2005 48 of 49 7.2 packaging data 7.3 ordering information parameter value package type 11mm x 11mm 100-ball lbga package drawing reference jedec m0192 moisture saturation level 3 junction to case thermal resistance, j-c 10.4c/w junction to air thermal resistance, j-a (at zero airflow) 37.1c/w psi 0.4c/w pb-free yes part number package pb-free temperature range GS1531-CBe2 100-ball bga yes 0c to 70c GS1531-CB 100-ball bga no 0c to 70c
caution electrostatic sensitive devices do not open packages or handle except at a static-free workstation gennum corporation mailing address: p.o. box 489, stn. a, burlington, ontario, canada l7r 3y3 shipping address: 970 fraser drive, burlington, ontario, canada l7l 5p5 tel. +1 (905) 632-2996 fax. +1 (905) 632-5946 gennum japan corporation shinjuku green tower building 27f, 6-14-1, nish i shinjuku, shinjuku-ku, tokyo, 160-0023 japan tel. +81 (03) 3349-5501, fax. +81 (03) 3349-5505 gennum uk limited 25 long garden walk, farnham, surrey, england gu9 7hx tel. +44 (0)1252 747 000 fax +44 (0)1252 726 523 gennum corporation assumes no liability for any errors or omissions in this document, or for the use of the circuits or devices described herein. the sale of the circuit or device described herein does not imply any patent license, and gennum makes no representation that the circuit or device is free from patent infringement. gennum and the g logo are registered trademarks of gennum corporation. ? copyright 2004 gennum corporation. all rights reserved. printed in canada. www.gennum.com gs1531 data sheet 30573 - 4 july 2005 49 49 of 49 document identification data sheet the product is in production. gen num reserves the right to make changes at any time to improve reliability, function or design, in order to provide the best product possible. 8. revision history version ecr date changes and / or modifications a 132588 january 2004 new document. b 133567 june 2004 modify supply voltage ranges and power dissipation. modify sdo section. add new solder reflow profile. apply new format. 0 134169 august 2004 modify electrical charac teristics based on charac terization of device. update text in section 2.4. modify sdo section and add resistor and capacitor values to r1 and c1 of typical application circuit. update to a preliminary data sheet. 1 134904 november 2004 changed interfacing resistor values between gs1531 and gs1528a on typical application circuit. added note for pclk jitter tolerance. added packaging data section. 2 136174 march 2005 update sclk to show as a burst clock. remove ?green? references. correct minor typing errors. 3 136663 may 2005 updated the status of the vd_std[4:0] and std_lock and int_progb bits following a device reset or the removal of the input pclk. changed the gspi input data hold time to a minimum instead of a maximum. 4 136981 july 2005 restored missing overli nes to pin names. added note on 59.94hz and 60hz formats to table 4-4 on page 29. corrected pclk to data timing (figure 4-1 on page 23). changed note on esd protection in absolute maximum ratings on page 13. corrected setup time and hold time labels in table 2-2 on page 14 and figure 4-1 on page 23. converted to data sheet.

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